High-speed demonstration of a superconducting pseudo-random bit-sequence generator
dc.contributor.author | Wang Z. | |
dc.contributor.author | Jeffery M.J. | |
dc.contributor.author | Perold W.J. | |
dc.contributor.author | Van Duzer T. | |
dc.date.accessioned | 2011-05-15T16:01:44Z | |
dc.date.available | 2011-05-15T16:01:44Z | |
dc.date.issued | 2000 | |
dc.description.abstract | This paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with complementary output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated using niobium technology with critical current density of 1 kA/cm2 and sheet resistance of 1 Ω/sq. The 4-bit PRBSG consists of 12 gates and its area is 1530×950 μm2. It has been fully tested with a three-phase power supply, and its power consumption is 0.15 mW. The correct operations have been verified experimentally at clock frequencies of up to 2 GHz. | |
dc.description.version | Article | |
dc.identifier.citation | IEEE Transactions on Applied Superconductivity | |
dc.identifier.citation | 10 | |
dc.identifier.citation | 2 | |
dc.identifier.issn | 10518223 | |
dc.identifier.other | 10.1109/77.848306 | |
dc.identifier.uri | http://hdl.handle.net/10019.1/12124 | |
dc.subject | Computer simulation | |
dc.subject | Monte Carlo methods | |
dc.subject | Complementary output switching logic (COSL) | |
dc.subject | Pseudorandom bit sequence generators (PRBSG) | |
dc.subject | Electric generators | |
dc.title | High-speed demonstration of a superconducting pseudo-random bit-sequence generator | |
dc.type | Article |