Complete Monte Carlo model description of lumped-element RSFQ logic circuits

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dc.contributor.authorFourie C.J.
dc.contributor.authorPerold W.J.
dc.contributor.authorGerber H.R.
dc.date.accessioned2011-05-15T16:01:43Z
dc.date.available2011-05-15T16:01:43Z
dc.date.issued2005
dc.description.abstractOver the last decade, Monte Carlo simulations have emerged as the most useful way of predicting the yield of RSFQ circuits, as they consider all manufacturing tolerance effects on a circuit, and are not restricted to bias current variations. Here we finally present a comprehensive definition of layout-extracted Monte Carlo model creation for lumped-element Spice simulations-from the local and global values for inductance, resistance and junction area from statistical models, to the inclusion of parasitics, layer-to-layer variations, variations in the penetration depth, and capacitance and mutual coupling. Finally, the addition of bias current trimming to the simulations to compensate for most global variations is described, and comparative yield results listed. © 2005 IEEE.
dc.description.versionConference Paper
dc.identifier.citationIEEE Transactions on Applied Superconductivity
dc.identifier.citation15
dc.identifier.citation2 PART I
dc.identifier.issn10518223
dc.identifier.other10.1109/TASC.2005.849856
dc.identifier.urihttp://hdl.handle.net/10019.1/12118
dc.subjectCapacitance
dc.subjectComputational complexity
dc.subjectInductance
dc.subjectJosephson junction devices
dc.subjectMathematical models
dc.subjectMonte Carlo methods
dc.subjectProbability distributions
dc.subjectSuperconducting devices
dc.subjectCircuit models
dc.subjectLayout extraction
dc.subjectMonte Carlo models
dc.subjectRSFQ
dc.subjectSpice models
dc.subjectYield production
dc.subjectLogic circuits
dc.titleComplete Monte Carlo model description of lumped-element RSFQ logic circuits
dc.typeConference Paper
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