Yield optimization of high frequency superconducting digital circuits with genetic algorithms
dc.contributor.author | Fourie C.J. | |
dc.contributor.author | Perold W.J. | |
dc.date.accessioned | 2011-05-15T16:00:42Z | |
dc.date.available | 2011-05-15T16:00:42Z | |
dc.date.issued | 2003 | |
dc.description.abstract | Even simple superconducting logic gates can contain tens of inductors, resistors and Josephson junctions. In order to increase the yield and reliability of such suboptimal circuits to acceptable levels, it is often needed to adjust all the element values. The search space is therefore very large, and genetic algorithms have been used with remarkable success to optimize such gates. Copyright © 2002 IEEE. | |
dc.description.version | Conference Paper | |
dc.identifier.citation | Transactions of the South African Institute of Electrical Engineers | |
dc.identifier.citation | 94 | |
dc.identifier.citation | 2 | |
dc.identifier.issn | 382221 | |
dc.identifier.uri | http://hdl.handle.net/10019.1/11837 | |
dc.subject | Electric inductors | |
dc.subject | Genetic algorithms | |
dc.subject | Logic gates | |
dc.subject | Optimization | |
dc.subject | Problem solving | |
dc.subject | Resistors | |
dc.subject | Superconducting devices | |
dc.subject | Switching | |
dc.subject | Complementary output switching logic (COSL) | |
dc.subject | Suboptimal circuits | |
dc.subject | Superconducting electronics | |
dc.subject | Yield optimization | |
dc.subject | Digital circuits | |
dc.title | Yield optimization of high frequency superconducting digital circuits with genetic algorithms | |
dc.type | Conference Paper |