Busbar design considerations for high power IGBT converters
dc.contributor.author | Beukes H.J. | |
dc.contributor.author | Enslin J.H.R. | |
dc.contributor.author | Spee R. | |
dc.date.accessioned | 2011-05-15T16:00:10Z | |
dc.date.available | 2011-05-15T16:00:10Z | |
dc.date.issued | 1997 | |
dc.description.abstract | This paper addresses an important issue in the design and synthesis of high power IGBT converters, i.e. the layout and design of connection busbars. Parasitic inductance, caused by the physical distance current has to flow from the storage capacitors to the static switches and back, is the major constraint in developing a bus structure. This leads to non-ideal converter operation, namely voltage overshoot, voltage drop and resonance with snubber capacitors. By analyzing the currents and fields in and around busbars, parasitic inductance can be predicted and limited. | |
dc.description.version | Conference Paper | |
dc.identifier.citation | PESC Record - IEEE Annual Power Electronics Specialists Conference | |
dc.identifier.citation | 2 | |
dc.identifier.issn | 2759306 | |
dc.identifier.uri | http://hdl.handle.net/10019.1/11559 | |
dc.subject | Bipolar transistors | |
dc.subject | Busbars | |
dc.subject | Capacitors | |
dc.subject | Circuit resonance | |
dc.subject | Electric network analysis | |
dc.subject | Electric network synthesis | |
dc.subject | Gates (transistor) | |
dc.subject | Integrated circuit layout | |
dc.subject | Insulated gate bipolar transistors (IGBT) | |
dc.subject | Parasitic inductance | |
dc.subject | Power converters | |
dc.title | Busbar design considerations for high power IGBT converters | |
dc.type | Conference Paper |