Optimised asynchronous timing for superconductive digital circuits

Simple item page
dc.contributor.authorGerber H.R.
dc.contributor.authorFourie C.J.
dc.contributor.authorPerold W.J.
dc.date.accessioned2011-05-15T16:00:41Z
dc.date.available2011-05-15T16:00:41Z
dc.date.issued2006
dc.description.abstractRapid Single Flux Quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of Gigahertz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and a asynchronous full adder was implemented and tested. Copyright © 2004 IEEE.
dc.description.versionArticle
dc.identifier.citationTransactions of the South African Institute of Electrical Engineers
dc.identifier.citation97
dc.identifier.citation3
dc.identifier.issn382221
dc.identifier.urihttp://hdl.handle.net/10019.1/11826
dc.subjectAsynchronous logic
dc.subjectAsynchronous timing
dc.subjectClock distribution
dc.subjectClock signal
dc.subjectComplex problems
dc.subjectFull adders
dc.subjectLow power application
dc.subjectOptimal timing
dc.subjectRapid single-flux quantum logic
dc.subjectRSFQ circuits
dc.subjectSelf-timing
dc.subjectSemiconductor design
dc.subjectSemiconductor technology
dc.subjectSuperconducting electronics
dc.subjectSynchronous clocking
dc.subjectUltra high speed
dc.subjectAdders
dc.subjectDigital integrated circuits
dc.subjectElectric clocks
dc.subjectIntegrated circuits
dc.subjectLogic gates
dc.subjectSemiconductor device manufacture
dc.subjectSuperconductivity
dc.subjectTime measurement
dc.subjectTiming circuits
dc.subjectLogic circuits
dc.titleOptimised asynchronous timing for superconductive digital circuits
dc.typeArticle
Files
Collections
Stellenbosch University - Scopus Publications