Simulated inductance variations in RSFQ circuit structures

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dc.contributor.authorFourie C.J.
dc.contributor.authorPerold W.J.
dc.date.accessioned2011-05-15T16:01:43Z
dc.date.available2011-05-15T16:01:43Z
dc.date.issued2005
dc.description.abstractManufacturing tolerances influence circuit parameters, and inductance is no exception. A computer application was developed to fully automate inductance calculation as part of a layout extraction suite. InductEx takes a GDSII layout file as input, finds the inductance ports, extracts structures, applies mask-to-wafer offsets and random process tolerances to the circuit structures, builds deck files that can be processed with FastHenry, and manages FastHenry - all autonomously. Results are presented for the simulated variation in inductance - both self and mutual, over hundreds of runs - in several common RSFQ structures in the Hypres 1 kA/cm2 process (with the latest tolerance values built in), even with the presence of moats. © 2005 IEEE.
dc.description.versionConference Paper
dc.identifier.citationIEEE Transactions on Applied Superconductivity
dc.identifier.citation15
dc.identifier.citation2 PART I
dc.identifier.issn10518223
dc.identifier.other10.1109/TASC.2005.849806
dc.identifier.urihttp://hdl.handle.net/10019.1/12115
dc.subjectComputer aided design
dc.subjectComputer simulation
dc.subjectElectric currents
dc.subjectFault tolerant computer systems
dc.subjectInductance
dc.subjectJosephson junction devices
dc.subjectMathematical models
dc.subjectMicrostrip lines
dc.subjectNormal distribution
dc.subjectFastHenry
dc.subjectInductance calculation
dc.subjectInductance variation
dc.subjectInductEx
dc.subjectMoats
dc.subjectIntegrated circuits
dc.titleSimulated inductance variations in RSFQ circuit structures
dc.typeConference Paper
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