High-speed demonstration of a superconducting pseudo-random bit-sequence generator

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dc.contributor.authorWang Z.
dc.contributor.authorJeffery M.J.
dc.contributor.authorPerold W.J.
dc.contributor.authorVan Duzer T.
dc.date.accessioned2011-05-15T16:01:44Z
dc.date.available2011-05-15T16:01:44Z
dc.date.issued2000
dc.description.abstractThis paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with complementary output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated using niobium technology with critical current density of 1 kA/cm2 and sheet resistance of 1 Ω/sq. The 4-bit PRBSG consists of 12 gates and its area is 1530×950 μm2. It has been fully tested with a three-phase power supply, and its power consumption is 0.15 mW. The correct operations have been verified experimentally at clock frequencies of up to 2 GHz.
dc.description.versionArticle
dc.identifier.citationIEEE Transactions on Applied Superconductivity
dc.identifier.citation10
dc.identifier.citation2
dc.identifier.issn10518223
dc.identifier.other10.1109/77.848306
dc.identifier.urihttp://hdl.handle.net/10019.1/12124
dc.subjectComputer simulation
dc.subjectMonte Carlo methods
dc.subjectComplementary output switching logic (COSL)
dc.subjectPseudorandom bit sequence generators (PRBSG)
dc.subjectElectric generators
dc.titleHigh-speed demonstration of a superconducting pseudo-random bit-sequence generator
dc.typeArticle
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