Code generation and simulation of an automatic, flexible QC-LDPC hardware decoder
| dc.contributor.advisor | Van Rooyen, Gert-Jan | en |
| dc.contributor.author | Von Leipzig, Mirko | en |
| dc.contributor.other | Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering. | en_ZA |
| dc.date.accessioned | 2015-05-20T09:27:51Z | |
| dc.date.available | 2015-05-20T09:27:51Z | |
| dc.date.issued | 2015-03 | en |
| dc.description | Thesis (MEng)--Stellenbosch University, 2015. | en_ZA |
| dc.description.abstract | ENGLISH ABSTRACT: Iterative error correcting codes such as LDPC codes have become prominent in modern forward error correction systems. A particular subclass of LDPC codes known as quasicyclic LDPC codes has been incorporated in numerous high speed wireless communication and video broadcasting standards. These standards feature multiple codes with varying codeword lengths and code rates and require a high throughput. Flexible hardware that is capable of decoding multiple quasi-cyclic LDPC codes is therefore desirable. This thesis investigates binary quasi-cyclic LDPC codes and designs a generic, flexible VHDL decoder. The decoder is further enhanced to automatically select the most likely decoder based on the initial a posterior probability of the parity-check equation syndromes. A software system is developed that generates hardware code for such a decoder based on a small user specification. The system is extended to provide performance simulations for this generated decoder. | en_ZA |
| dc.description.abstract | AFRIKAANSE OPSOMMING: Iteratiewe foutkorreksiekodes soos LDPC-kodes word wyd gebruik in moderne voorwaartse foutkorreksiestelsels. ’n Subklas van LDPC-kodes, bekend as kwasisikliese LDPC-kodes, word in verskeie hoëspoed-kommunikasie- en video-uitsaaistelselstandaarde gebruik. Hierdie standaarde inkorporeer verskeie kodes van wisselende lengtes en kodetempos, en vereis hoë deurset. Buigsame apparatuur, wat die vermoë het om ’n verskeidenheid kwasisikliese LDPC-kodes te dekodeer, is gevolglik van belang. Hierdie tesis ondersoek binêre kwasisikliese LDPC-kodes, en ontwerp ’n generiese, buigsame VHDL-dekodeerder. Die dekodeerder word verder verbeter om outomaties die mees waarskynlike dekodeerder te selekteer, gebaseer op die aanvanklike a posteriori-waarskynlikheid van die pariteitstoetsvergelykings se sindrome. ’n Programmatuurstelsel word ontwikkel wat die fermware-kode vir so ’n dekodeerder genereer, gebaseer op ’n beknopte gebruikerspesifikasie. Die stelsel word uitgebrei om werksverrigting te simuleer vir die gegenereerde dekodeerder. | af_ZA |
| dc.format.extent | 90 pages : illustrations | en_ZA |
| dc.identifier.uri | http://hdl.handle.net/10019.1/96835 | |
| dc.language.iso | en_ZA | en_ZA |
| dc.publisher | Stellenbosch : Stellenbosch University | en_ZA |
| dc.rights.holder | Stellenbosch University | en_ZA |
| dc.subject | Quasi-cyclic low-density parity check (QC-LDPC) | en_ZA |
| dc.subject | Hardware decoder -- Code generation and simulation | en_ZA |
| dc.title | Code generation and simulation of an automatic, flexible QC-LDPC hardware decoder | en_ZA |
| dc.type | Thesis | en_ZA |