Layout-to-schematic extraction as a tool to be used in layout versus schematic verification of RSFQ circuits
dc.contributor.author | Roberts RMC | |
dc.contributor.author | Fourie CJ | |
dc.date.accessioned | 2014-07-06T17:27:09Z | |
dc.date.available | 2014-07-06T17:27:09Z | |
dc.date.issued | 2013 | |
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dc.description | Ingenieurswese | |
dc.description | Elektriese En Elektroniese Ingenie | |
dc.identifier.citation | 898 | |
dc.identifier.citation | 902 | |
dc.identifier.uri | http://hdl.handle.net/10019.1/89253 | |
dc.publisher | IEEE | |
dc.title | Layout-to-schematic extraction as a tool to be used in layout versus schematic verification of RSFQ circuits | |
dc.type | Proceedings International |