Accelerating the method of moments implementation on FPGA hardware

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dc.contributor.advisorLudick, Danieen_ZA
dc.contributor.advisorBarnard, Arnoen_ZA
dc.contributor.authorMnisi, Caleben_ZA
dc.contributor.otherStellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.en_ZA
dc.date.accessioned2021-10-12T07:39:33Z
dc.date.accessioned2021-12-22T14:16:23Z
dc.date.available2021-10-12T07:39:33Z
dc.date.available2021-12-22T14:16:23Z
dc.date.issued2021-12
dc.descriptionThesis (MEng)--Stellenbosch University, 2021.en_ZA
dc.description.abstractENGLISH ABSTRACT: Advances in transistor technology have reached a point where the physical limitations on chip design means that we are starting to approach a decline in the curve that used to follow Moore’s law. Engineers and Scientists are now turning to Hyper-Scale computing and parallel systems to be able to continue the trend of Moore’s law and offset this decreased cadence. This naturally means that the traditional way of running operations also has to be revised to facilitate implementation on parallel systems. This project aims to develop hardware architecture that optimizes the computation of electromagnetic problems using the Method of Moments (MoM) formulation on field programmable gate array (FPGA) hardware. This can be accomplished by exploiting inherent properties in the formulation that allow for parallel computation of independent sections, and then running these computations in parallel, using dedicated computation units on the FPGA fabric. FPGAs and reconfigurable systems provide a combination of low power consumption and flexibility for applications in computation. We aim to exploit the reconfigurable structure of the FPGA to help facilitate the development of the hardware architecture. The configurable interconnect of the FPGA also allows us to arrange the FPGA resources in a manner that will optimize the specific computation and thus reduce the computation time.en_ZA
dc.description.abstractAFRIKAANSE OPSOMMING: Vooruitgang in transistor tegnologie het ’n punt bereik waar die fisiese beperkings van rekenaarskyfie ontwerp beteken dat daar ’n afname waargeneem word in die kurwe wat voorheen Moore se wet gevolg het. Ingenieurs en wetenskaplikes het nou begin om hiperskaalse rekenaar en parallelle stelsels aan te wend om dit moontlik te maak om die neiging van die wet van Moore te kan voortsit en hierdie verlaagde kadens teen te werk. Dit beteken dat die tradisionele manier van rekenaarstelsel bestuur ook hersien moet word om die implementering van parallelle stelsels te vergemaklik. Hierdie projek het die einddoel om ’n hardeware argitektuur te ontwikkel wat die oplossing van elektromagnetiese probleme met behulp van die Moment Metode (MoM) formulering op FPGAs optimeer. Hierdie doel kan bereik word deur van die inherente eienskappe van die MoM formulering wat voorsiening maak vir parallelle berekening van onafhanklike afdelings gebruik te maak. Hierdie onafhanklike afdelings kan in parallel uitgevoer word met behulp van die toegewyde berekening eenhede van die FPGA. FPGAs en herkonfigureerbare stelsels bied ’n kombinasie van van hoë rekenaarkrag en die gemak vir toepassings in berekening. Ons mik om die herkonfigureerbare struktuur van die FPGA aan te wend om die ontwikkeling van die hardeware-argitektuur te vergemaklik. Die konfigureerbare interkonneksies van die FPGA stel ons ook in staat om die FPGA hulpbronne op so ’n manier aan te wend om die toepaslike berekeninge te optimeer en dus berekeningstyd te verminder.af_ZA
dc.description.versionMastersen_ZA
dc.format.extent100 pagesen_ZA
dc.identifier.urihttp://hdl.handle.net/10019.1/123696
dc.language.isoen_ZAen_ZA
dc.publisherStellenbosch : Stellenbosch Universityen_ZA
dc.rights.holderStellenbosch Universityen_ZA
dc.subjectUCTDen_ZA
dc.subjectTransistorsen_ZA
dc.subjectMoore's lawen_ZA
dc.subjectTechnological innovations -- Forecastingen_ZA
dc.subjectField Programmable Gate Arrayen_ZA
dc.subjectProgrammable logic devicesen_ZA
dc.titleAccelerating the method of moments implementation on FPGA hardwareen_ZA
dc.typeThesisen_ZA
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