Parameter extraction of superconducting integrated circuits
| dc.contributor.advisor | Perold, W. J. | |
| dc.contributor.author | Lotter, Pierre | en_ZA |
| dc.contributor.other | University of Stellenbosch. Faculty of Engineering. Dept. of Electrical and Electronic Engineering. | |
| dc.date.accessioned | 2008-02-05T09:45:36Z | en_ZA |
| dc.date.accessioned | 2010-06-01T08:29:46Z | |
| dc.date.available | 2008-02-05T09:45:36Z | en_ZA |
| dc.date.available | 2010-06-01T08:29:46Z | |
| dc.date.issued | 2006-12 | en_ZA |
| dc.description | Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006. | |
| dc.description.abstract | Integrated circuits are expensive to manufacture and it is important to verify the correct operation of a circuit before fabrication. Efficient, though accurate, parameter extraction of post-layout designs are required for estimation of circuit success rates. This thesis discusses electrical netlist and fast parameter extraction techniques suited for both intraand inter-gate connections. This includes the use of extraction windows and look-up tables (LUTs) for accurate inductance and capacitance estimation. These techniques can readily be implemented in automated layout software where fast parameter extraction is required for timing analysis and gate placement. | en_ZA |
| dc.format.extent | 1408363 bytes | en_ZA |
| dc.format.mimetype | application/pdf | en_ZA |
| dc.identifier.uri | http://hdl.handle.net/10019.1/1652 | |
| dc.language.iso | en | en_ZA |
| dc.publisher | Stellenbosch : University of Stellenbosch | |
| dc.rights.holder | University of Stellenbosch | |
| dc.subject | Superconductivity | en_ZA |
| dc.subject | Dissertations -- Electronic engineering | en_ZA |
| dc.subject | Theses -- Electronic engineering | en_ZA |
| dc.subject.other | Electrical and Electronic Engineering | en_ZA |
| dc.title | Parameter extraction of superconducting integrated circuits | en_ZA |
| dc.type | Thesis | en_ZA |