Low impedance characterisation and modeling of high power LDMOS devices
Date
2005-12
Authors
Malan, Pieter Jacob De Villiers
Journal Title
Journal ISSN
Volume Title
Publisher
Stellenbosch : University of Stellenbosch
Abstract
In RF power transistor characterisation, the designer is confronted with low impedance
measurements (typically from 1 Ohm to 12 Ohm). These transistors are contained in
metal-ceramic packages of which the lead widths vary with power capability. This thesis
presents a high-quality fixture design with low impedance TRL calibration standards for
characterisation of an LDMOS transistor. Pre-matching networks are used to transform
to the low impedance environment. Since these pre-matching networks are independent
of the termination impedance, the low impedance port can always be designed to comply
with the same dimension as the device which is being measured.
Description
Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005.
Keywords
Low Impedance, Load Line Method, TRL (Thru-Reflect-Line), Calibration, Substrate Parameter Extraction, Small-Signal Parameter Extraction, Power amplifier, LDMOS, Dissertations -- Electrical and electronic engineering, Theses -- Electrical and electronic engineering