Monte Carlo optimization of superconducting complementary output switching logic circuits
dc.contributor.author | Jeffery M. | |
dc.contributor.author | Perold W.J. | |
dc.contributor.author | Wang Z. | |
dc.contributor.author | Van Duzer T. | |
dc.date.accessioned | 2011-05-15T16:01:44Z | |
dc.date.available | 2011-05-15T16:01:44Z | |
dc.date.issued | 1998 | |
dc.description.abstract | The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix. © 1998 IEEE. | |
dc.description.version | Article | |
dc.identifier.citation | IEEE Transactions on Applied Superconductivity | |
dc.identifier.citation | 8 | |
dc.identifier.citation | 3 | |
dc.identifier.issn | 10518223 | |
dc.identifier.uri | http://hdl.handle.net/10019.1/12125 | |
dc.subject | Computer simulation | |
dc.subject | Integrated circuit testing | |
dc.subject | Logic circuits | |
dc.subject | Logic design | |
dc.subject | Monte Carlo methods | |
dc.subject | Optimization | |
dc.subject | Timing circuits | |
dc.subject | Complementary output switching logic (COSL) | |
dc.subject | Multivariable threshold logic (MVTL) circuits | |
dc.subject | Software package HSPICE | |
dc.subject | Superconducting integrated circuits | |
dc.subject | Superconducting devices | |
dc.title | Monte Carlo optimization of superconducting complementary output switching logic circuits | |
dc.type | Article |