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Reconfigurable logic for array processing

dc.contributor.authorBakkes P.I.
dc.contributor.authordu Plessis J.J.
dc.date.accessioned2011-05-15T15:53:43Z
dc.date.available2011-05-15T15:53:43Z
dc.date.issued1996
dc.identifier.citationIEEE AFRICON Conference
dc.identifier.citation2
dc.identifier.urihttp://hdl.handle.net/10019.1/8776
dc.description.abstractIn this paper the architecture of the MIX system is described. It was designed to investigate some of the factors involved in approving reconfigurable and/or fixed logic in a typical engineering algorithm. A matrix-vector multiplier of 32 bit floating point numbers, is used as a vehicle for the investigation. The results indicate that fixed logic is more suited for floating point units and memories while reconfigurable logic is useful for implementing control logic providing significant flexibility. It is also found that the additional delay in reconfigurable logic can very effectively overlap with the operating time of the fixed logic subsystems. The advantage of reconfigurability of the control is therefore combined with the high bandwidth properties of the fixed logic.
dc.titleReconfigurable logic for array processing
dc.typeConference Paper
dc.description.versionConference Paper


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