Simulated inductance variations in RSFQ circuit structures
Date
2005
Authors
Fourie C.J.
Perold W.J.
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
Manufacturing tolerances influence circuit parameters, and inductance is no exception. A computer application was developed to fully automate inductance calculation as part of a layout extraction suite. InductEx takes a GDSII layout file as input, finds the inductance ports, extracts structures, applies mask-to-wafer offsets and random process tolerances to the circuit structures, builds deck files that can be processed with FastHenry, and manages FastHenry - all autonomously. Results are presented for the simulated variation in inductance - both self and mutual, over hundreds of runs - in several common RSFQ structures in the Hypres 1 kA/cm2 process (with the latest tolerance values built in), even with the presence of moats. © 2005 IEEE.
Description
Keywords
Computer aided design, Computer simulation, Electric currents, Fault tolerant computer systems, Inductance, Josephson junction devices, Mathematical models, Microstrip lines, Normal distribution, FastHenry, Inductance calculation, Inductance variation, InductEx, Moats, Integrated circuits
Citation
IEEE Transactions on Applied Superconductivity
15
2 PART I
15
2 PART I