A switching logic digitizer for analog-to-digital conversion
Date
2007
Authors
Powell I.A.
Perold W.J.
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Journal ISSN
Volume Title
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Abstract
The design and simulation of a complementary output switching logic (COSL) compatible, voltage state, switching logic comparator (SLC), and a flash analog-to-digital converter (ADC) for high-speed applications, with multigigahertz input bandwidth, is presented. A detailed design for the SLC is provided and verified with simulations. The comparator is then optimized utilizing Monte Carlo yield predictions. The optimized comparator is incorporated into the construction of a 4-bit quantizer of an ADC. The Gray-code output is converted into binary using COSL gates. The functionality, linearity, maximum input bandwidth, and dynamic range of the 4-bit ADC is verified by simulation, using a number of special input waveforms. The performance of the comparator and the 4-bit ADC are also evaluated with thermal noise incorporated into simulations. Beat frequency simulations and Fourier spectra are also used in the evaluation of the ADC performance. A fully functional 4-bit ADC, with a maximum input bandwidth of 10 GHz for a clock speed of 20 GHz, was achieved through simulations. Beat frequency simulations revealed that the comparators have an input bandwidth greater than 19 GHz with sufficient dynamic range for an ADC of greater than 6 bits of resolution. Due to the fact that the aperture time for the ADC is dependent on the rise time of the sampling pulse and not the width of the pulse, a much smaller aperture time is obtained which directly translates to higher input bandwidth. © 2006 IEEE.
Description
Keywords
Comparator circuits, Computer simulation, Electric potential, Monte Carlo methods, Superconducting devices, Thermal noise, Complementary output switching logic (COSL), Frequency simulations, Monte Carlo yield optimization, Analog to digital conversion
Citation
IEEE Transactions on Applied Superconductivity
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