A reconfigurable array processor

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dc.contributor.authorBakkes, P. J.en_ZA
dc.contributor.otherStellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.en_ZA
dc.date.accessioned2012-08-27T11:36:50Z
dc.date.available2012-08-27T11:36:50Z
dc.date.issued1996-03
dc.descriptionThesis (PhD)--University of Stellenbosch, 1996.
dc.description.abstractENGLISH ABSTRACT: This dissertation reports on an investigation of the trade-off of the properties of presently available fixed and reconfigurable logic to find an optimal use for both types of logic in a typical engineering application. The research vehicle is a 32 bit floating point matrix-vector array processor. The system named MIX is designed, simulated, built and tested and the results are evaluated. Simulation and synthesis tools are used to extensively and a firm base for further research is established. State machines are implemented with a shift register technique developed earlier by the author. The results prove that fixed logic is most suited for subsystems such as memories and floating point units where reconfiguration is not necessarily required, but high logic density and speed are essential. Reconfigurable logic proves most useful for control functions and simple data manipulation. Delays resulting form the routing of data through the reconfigurable logic, as hidden by using pipeline techniques. It is proven that the performance of a mixed logic system approaches that of a pure fixed logic implementation, if the design allows the overlap of the execution of functions in the fixed and reconfigurable subsystems.en_ZA
dc.description.abstractAFRIKAANSE OPSOMMING: Hierdie verhandeling rapporteer oor 'n ondersoek van die afspeel van die eienskappe van huidig beskikbare vast en herkonfigureerbare logika om 'n optimale gebruik te vind vir beide tipe logika in 'n tipiese ingenieurs toepassing. Die voertuig vir die navorsing is 'n 32 bis wisselpunt matriks-vektor verwerker. Die MIX stelsel is ontwerp, gesimuleer, gebou en die resultate geevalueer. Simulasie en sintese gereedskap word vryelik gebruik en 'n ferm basis vir verder navorsing is geskep. Toestandmasjiene is met 'n skuifregistertegniek, wat vroeër deur die skrywer ontwikkel is, geïmplimenteer. Die resultate bewys dat vast logika mees geskik is vir substelsels, soos geheue en wisselpuntverwerkers, waar herkonfigurasie nie noodwendig benodig word nie maar hoe digtheid en spoed essensieël is. Herkonfiguureerbare logika is mees bruikbaar vir beheer en eenvoudige data manupilasie funksies. Die vertraging a.g.v. die roetering van data deur herkonfigureerbare logika, word versteek deur van pyplyn tegnieke gerbuik te maak. Dit word bewys dat die werkverrigting van 'n stelsel, met 'n mengsel van vaste en herkonfigureerbare logika, die van die stelsel met slegs vaste logika benader, indien die ontwerp toelaat dat uitvoering van funksies in die vaste en herkonfigureerbare substelsels in tyd oorvleuel.af_ZA
dc.description.versionDoctoralen_ZA
dc.format.extent138 pages : illustrationsen_ZA
dc.identifier.urihttp://hdl.handle.net/10019.1/54996
dc.language.isoen_ZAen_ZA
dc.publisherStellenbosch : Stellenbosch Universityen_ZA
dc.rights.holderStellenbosch Universityen_ZA
dc.subjectArray processorsen_ZA
dc.subjectField programmable gate arraysen_ZA
dc.subjectMicroprogrammingen_ZA
dc.titleA reconfigurable array processoren_ZA
dc.typeThesis
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