CMOS based Decision Directed Costas Carrier Recovery Loop (DDC-CRL) for a DSSS communication system
dc.contributor.author | Naude N. | |
dc.contributor.author | Linde L.P. | |
dc.contributor.author | Sinha S. | |
dc.date.accessioned | 2011-05-15T15:53:35Z | |
dc.date.available | 2011-05-15T15:53:35Z | |
dc.date.issued | 2007 | |
dc.description.abstract | For the discussed DSSS (direct sequence spread spectrum) communication system to be successful, accurate carrier recovery and phase estimation are required in the receiver. This paper presents an analogue DDC-CRL which performs both of these functions as well as the despreading, demodulation and bit detection operations performed by an ideal DSSS receiver. The DDC-CRL presented in this paper operates at bit rates up to 1.53 Mbps and accommodates arbitrary sequence length. The loop operates anywhere over a 20 MHz bandwidth within the 2.4 GHz to 2.4835 GHz ISM (industrial, scientific and medical) band. The DDC-CRL is designed for the 0.35 ?m CMOS process from Austria Microsystems (AMS). ©2007 IEEE. | |
dc.description.version | Conference Paper | |
dc.identifier.citation | IEEE AFRICON Conference | |
dc.identifier.other | 10.1109/AFRCON.2007.4401590 | |
dc.identifier.uri | http://hdl.handle.net/10019.1/8689 | |
dc.title | CMOS based Decision Directed Costas Carrier Recovery Loop (DDC-CRL) for a DSSS communication system | |
dc.type | Conference Paper |