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Parameter extraction of superconducting integrated circuits

dc.contributor.advisorPerold, W. J.
dc.contributor.authorLotter, Pierreen_ZA
dc.contributor.otherUniversity of Stellenbosch. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.
dc.date.accessioned2008-02-05T09:45:36Zen_ZA
dc.date.accessioned2010-06-01T08:29:46Z
dc.date.available2008-02-05T09:45:36Zen_ZA
dc.date.available2010-06-01T08:29:46Z
dc.date.issued2006-12en_ZA
dc.identifier.urihttp://hdl.handle.net/10019.1/1652
dc.descriptionThesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006.
dc.description.abstractIntegrated circuits are expensive to manufacture and it is important to verify the correct operation of a circuit before fabrication. Efficient, though accurate, parameter extraction of post-layout designs are required for estimation of circuit success rates. This thesis discusses electrical netlist and fast parameter extraction techniques suited for both intraand inter-gate connections. This includes the use of extraction windows and look-up tables (LUTs) for accurate inductance and capacitance estimation. These techniques can readily be implemented in automated layout software where fast parameter extraction is required for timing analysis and gate placement.en_ZA
dc.format.extent1408363 bytesen_ZA
dc.format.mimetypeapplication/pdfen_ZA
dc.language.isoenen_ZA
dc.publisherStellenbosch : University of Stellenbosch
dc.subjectSuperconductivityen_ZA
dc.subjectDissertations -- Electronic engineeringen_ZA
dc.subjectTheses -- Electronic engineeringen_ZA
dc.subject.otherElectrical and Electronic Engineeringen_ZA
dc.titleParameter extraction of superconducting integrated circuitsen_ZA
dc.typeThesisen_ZA
dc.rights.holderUniversity of Stellenbosch


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