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A Physical Design verification framework for superconducting electronics

dc.contributor.advisorFourie, Coenrad J.en_ZA
dc.contributor.authorVan Staden, Rubenen_ZA
dc.contributor.otherStellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.en_ZA
dc.date.accessioned2019-11-19T04:58:22Z
dc.date.accessioned2019-12-11T06:47:19Z
dc.date.available2019-11-19T04:58:22Z
dc.date.available2019-12-11T06:47:19Z
dc.date.issued2019-12
dc.identifier.urihttp://hdl.handle.net/10019.1/107100
dc.descriptionThesis (PhD)--Stellenbosch University, 2019.en_ZA
dc.description.abstractENGLISH ABSTRACT: A new parameterized methodology for solving physical design verification for superconductor digital electronics (SDE) is proposed. Circuit verification tools forms an important part in integrated circuit (IC) design. This dissertation introduces a new physical verification framework, called SPiRA, that is composed of three modules: Parameterized Cells (PCells), Design Rule Checking (DRC) and Layout-versus-Schematic (LVS). These form part of the electronic design automation (EDA) verification toolchain for SDE. The proposed framework uses a combination of Python and metaprogramming to create a modular approach to verifying SDE circuits. The goal of the PCells framework is to create efficient layout generators for superconductor electronics, while at the same time checking for design rule violations. The LVS module is responsible for verifying if the designed circuit layout corresponds to the original simulated schematic. Parameter extraction for superconductor circuit technologies, such as single flux quantum (SFQ), requires an input netlist that corresponds to the circuit layout. The parameter extraction model is only as good as the given netlist, which makes LVS an essential piece in the parameter extraction phase. The proposed LVS module uses a parameterizedhierarchical methodology, which is process independent. The framework is capable of supporting any kind of superconducting- or quantum circuit technology, such as Rapid-Single-Flux-Quantum (RSFQ), Energy-effiecient RSFQ (ERSFQ, eSFQ) or Adiabatic Quantum Flux Parametron (AQFP).en_ZA
dc.description.abstractAFRIKAANSE OPSOMMING: n Nuwe geparameteriseerde metode vir die oplos van fisiese ontwerp verifikasie vir supergeleier digitale elektronika (SDE) word voorgestel. Stroombaan verifikasie gereedskap vorm ’n belangrike deel in die geïntegreerde stroombaan (IC) ontwerp. Hierdie desertasie stel bekend ’n nuwe fisiese verifikasie raamwerk, genaamd SPiRA, wat bestaan uit drie modules: "Parameterized Cells (PCells)", "Design Rule Checking (DRC)", en "Layout-versus-Schematic (LVS)". Dit maak deel van die elektroniese ontwerp outmatisering (EDA) verifikasie sagteware vir SDE. Die voorgestelde raamwerk gebruik ’n kombinasie van Python en meta-programming om ’n modulere benadering te skep om SDE-stroombane te verifieer. Die doel van die PCell-raamwerk is om doeltreffende uitleggenerators vir supergeleier electronika te skep, terwyl ontwerpreël oortredings terselfdetyd nagegaan word. Die LVS-module is verantwoordelik vir die verifiëring van die ontwerpuitleg en bepaal of dit ooreenstem met die oorspronklike gesimuleerde uitleg. Parameteronttrekking vir supergeleier stroombaan tegnologie, soos "Single Flux Quantum (SFQ)", vereis dat ’n stroombaan ooreenstem met die fisiese uitleg. Die akkuraatheid van die parameter ekstraksie model word grootliks bepaal deur die gegewe stroombaan, daarom is LVS ’n noodsaaklike aspek in die parameter ontrekking fase. Die voorgestelde LVS-module gebruik ’n parameter-hierargiese metodologie, wat proses onafhanklik is. Die raamwerk is in staat om enige soort supergeleidende stroombaan tegnologie te ondersteun, soos Rapid-Single-Flux-Quantum (RSFQ), Energie-effektiewe RSFQ (ERSFQ, eSFQ) of Adiabatic Quantum Flux Parametron (AQFP).af_ZA
dc.format.extent198 pages : illustrationsen_ZA
dc.language.isoen_ZAen_ZA
dc.subjectHardware verificationen_ZA
dc.subjectElectric lines -- Superconductingen_ZA
dc.subjectCircuits, Electricen_ZA
dc.titleA Physical Design verification framework for superconducting electronicsen_ZA
dc.typeThesisen_ZA
dc.description.versionDoctoralen_ZA


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