Digitally controlled class-D audio amplifier

Van der Merwe, Carel (2017-03)

Thesis (MEng)--Stellenbosch University, 2017.

Thesis

ENGLISH ABSTRACT: Class-D audio ampli ers have become increasingly popular due to the fact that they use transistors as switches to amplify audio and do not operate them in their linear region, as is the case with other classes of ampli ers. This ensures that class-D ampli ers have very high e ciencies, making them a lot smaller than their counterparts. Traditionally, class-D ampli ers have been controlled using analogue circuits. This thesis will discuss the digital control of a class-D ampli er. The goal is to implement the ampli er using only a switching output stage, demodulation lter, simple analogue-todigital converter and an FPGA with peripheral components. This will make it possible for further work to reduce the ampli er to a single integrated circuit and output stage, making it even more compact than its analogue-controlled counterpart while maintaining equivalent performance. The controller design is done in the z-domain with the PWM modelled as a sampling operation. A mathematical expression is obtained to determine the PWM input signal from which the comparator small-signal gain is calculated. Ripple compensation is implemented to ensure that the comparator small-signal gain remains constant. The main challenge in the controller design is adequately attenuating the quantization noise, which is induced into the system by the digital PWM and the analogue-to-digital converter. This is done by ensuring that the system has a high gain across the audio band (20 Hz to 20 kHz). Simulations are done in an environment emulating that of the FPGA. VHDL is used to practically implement the controller. A system setup is constructed using pre-designed hardware and experimental results are presented.

AFRIKAANSE OPSOMMING: Klas-D klank versterkers het onlangs baie populêr begin raak te danke aan die feit dat hulle seine versterk deur transistors as skakelaars te gebruik. Ander klasse van versterkers dryf gewoonlik transistors aan in hul lineêre gebied. Klas-D versterkers is dus baie meer e ektief as ander versterkers wat veroorsaak dat hulle baie kleiner gemaak kan word as die van ander klasse. Klas-D klank versterkers word tradisioneel beheer deur analoog bane. Hierdie tesis behels die digitale beheer van 'n klas-D klank versterker. Die doel is om die versterker te implementeer deur net 'n uittreestadium, demodulasie lter, analoog-na-digitaal omsetter en FPGA te gebruik. Dit sal dit moontlik maak om in toekomstige werk die versterker te implementeer deur slegs 'n uittreestadium en 'n enkele geïntegreerde stroombaan te gebruik. Hierdie sal die versterker nog kleiner as sy analoog beheerde eweknie maak, terwyl dit ekwivalente verrigting handhaaf. Die beheerder ontwerp is in die z-vlak gedoen waar die PWM gemodelleer word as 'n monster operasie. 'n Wiskundige uitdrukking is afgelei om die PWM intreesein te bereken. Hierdie uitdrukking word dan gebruik om die kleinseinaanwins van die vlakvergelyker te bereken. Ri elkompensasie word geïmplimenteer om te verseker dat die kleinseinaanwins konstant bly. Die hoof uitdaging van die beheerder ontwerp is om die kwantiseringsruis, wat deur die digitale PWM en die analoog-na-digitaal omsetter veroorsaak word, genoeg te onderdruk. Hierdie word bereik deur te verseker dat die sisteem 'n hoë aanwins het oor die hele klank spektrum (20 Hz - 20 kHz). Simulasies word gedoen in 'n omgewing wat die van die FPGA naboots en VHDL word gebruik om die beheerder prakties te implementeer. Die sisteem word gebou uit voorheen ontwikkelde hardware en eksperimentele resultate word getoonset.

Please refer to this item in SUNScholar by using the following persistent URL: http://hdl.handle.net/10019.1/100881
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