Accelerated simulation technique for low bit error probability estimation of rapid single flux quantum logic cells
Date
2007
Authors
Hardie G.L.
Perold W.J.
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
The elevated operating temperatures of high-Tc superconductor (HTS) rapid single flux quantum (RSFQ) logic cells lead to higher thermal noise and this can be a major limiting factor in the development of working circuits of this kind. Determining the thermally induced bit error probability (BEP) of a circuit is therefore extremely important. If the BEP of a circuit is high enough it can be directly measured by running a circuit simulation over many clock cycles and counting the faulty bits. However, the BEP's required are very low and these simulations take enormous amounts of time. We propose a general method that can be applied to any circuit, to quickly and easily determine its BEP, without requiring the identification of any specific error-prone junctions or the understanding, application and solving of any complicated and computationally intensive mathematical formulas. By varying the temperature that a circuit is simulated at, the amount of noise introduced into the system can be controlled: the higher the temperature, the more noise introduced, and the higher the observed BEP. The BEP is measured at various higher-than-normal temperatures where it can be measured quickly and relatively accurately, and a parametric model is then fitted to the data collected that describes the BEP as a function of temperature. Extrapolation of this model estimates the BEP at the required operating temperature. © 2007 IEEE.
Description
Keywords
Bit error rate, Circuit simulation, Computational complexity, Data acquisition, Error analysis, Networks (circuits), Thermal noise, Clock cycles, Logic cells, RSFQ, Single flux quantum, Working circuits, High temperature superconductors
Citation
IEEE Transactions on Applied Superconductivity
17
2
17
2