Department of Electrical and Electronic Engineering
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Electrical and Electronic Engineering is an exciting and dynamic field. Electrical engineers are responsible for the generation, transfer and conversion of electrical power, while electronic engineers are concerned with the transfer of information using radio waves, the design of electronic circuits, the design of computer systems and the development of control systems such as aircraft autopilots. These sought-after engineers can look forward to a rewarding and respected career.
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Browsing Department of Electrical and Electronic Engineering by browse.metadata.advisor "Barnard, Arno"
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- ItemAccelerating the method of moments implementation on FPGA hardware(Stellenbosch : Stellenbosch University, 2021-12) Mnisi, Caleb; Ludick, Danie; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: Advances in transistor technology have reached a point where the physical limitations on chip design means that we are starting to approach a decline in the curve that used to follow Moore’s law. Engineers and Scientists are now turning to Hyper-Scale computing and parallel systems to be able to continue the trend of Moore’s law and offset this decreased cadence. This naturally means that the traditional way of running operations also has to be revised to facilitate implementation on parallel systems. This project aims to develop hardware architecture that optimizes the computation of electromagnetic problems using the Method of Moments (MoM) formulation on field programmable gate array (FPGA) hardware. This can be accomplished by exploiting inherent properties in the formulation that allow for parallel computation of independent sections, and then running these computations in parallel, using dedicated computation units on the FPGA fabric. FPGAs and reconfigurable systems provide a combination of low power consumption and flexibility for applications in computation. We aim to exploit the reconfigurable structure of the FPGA to help facilitate the development of the hardware architecture. The configurable interconnect of the FPGA also allows us to arrange the FPGA resources in a manner that will optimize the specific computation and thus reduce the computation time.
- ItemAutomated coverage calculation and test case generation(Stellenbosch : Stellenbosch University, 2012-03) Morrison, George Campbell; Inggs, Cornelia P.; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic EngineeringENGLISH ABSTRACT: This research combines symbolic execution, a formal method of static analysis, with various test adequacy criteria, to explore the e ectiveness of using symbolic execution for calculating code coverage on a program's existing JUnit test suites. Code coverage is measured with a number of test adequacy criteria, including statement coverage, branch coverage, condition coverage, method coverage, class coverage, and loop coverage. The results of the code coverage calculation is then used to automatically generate JUnit test cases for areas of a program that are not su ciently covered. The level of redundancy of each test case is also calculated during coverage calculation, thereby identifying fully redundant, and partially redundant, test cases. The combination of symbolic execution and code coverage calculation is extended to perform coverage calculation during a manual execution of a program, allowing testers to measure the e ectiveness of manual testing. This is implemented as an Eclipse plug-in, named ATCO, which attempts to take advantage of the Eclipse workspace and extensible user interface environment to improve usability of the tool by minimizing the user interaction required to use the tool. The code coverage calculation process uses constraint solving to determine method parameter values to reach speci c areas in the program. Constraint solving is an expensive computation, so the tool was parallellised using Java's Concurrency package, to reduce the overall execution time of the tool.
- ItemA CAN based distributed telemetry and telecommand network for a nanosatellite(Stellenbosch : Stellenbosch University, 2008-03) Khumalo, Simphiwe; Steyn, W. H.; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.A communications protocol is designed for real time control and data handling for a Nanosatellite application. The communication protocol is based on the Controller Area Network (CAN) technology. The protocol handles different message types such as time synchronization, telecommand messages, telemetry acquisition, unsolicited telemetry messages, large file transfers and debug messages. The design of the protocol entails finding a suitable target microcontroller in which the protocol implementation is demonstrated. This requires consideration of a number of development factors such as cost, complexity, availability, reliability and operational environment (space). The AVR AT90CAN128 microcontroller was chosen as a target microcontroller as it gave most of the required factors mentioned above. The protocol implementation involves developing low level software drivers, the middleware and the application programs to demonstrate handling of each supported message. In the implementation the media access scheme and low layer communication is provided by the CAN low level kernel (physical and data link layers). The protocol performance was evaluated by measuring the software response latencies, the bus throughputs and the software efficiencies. Power consumption due to CAN communication was also measured. System reliability was tested by loading the CAN bus with extreme communication traffic and letting the system run for a long time. The observation was that messages were handled consistently.
- ItemDeveloping a test suite to aid in single event effect testing of ARM microcontrollers(Stellenbosch : Stellenbosch University, 2021-03) Sciocatti, Victor J.; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: This thesis presents a test suite's design and development that can easily integrate Arm Cortex-M, specifically the STMicroelectronics STM32-range, into the SEE test environment at iThemba Labs with minimal effort from the testers. It can also help local satellite designers verify the resistivity of their designs to Single Event Effects (SEE), even with minimal, or no, SEE test data for their specific Device-Under-Test (DUT). A concept design for such a system is done, and an iterative approach is followed to implement this system. The validity of using JTAG to extract or inject data into the DUTs is investigated. A custom JTAG driver is reverse-engineered and implemented to be able to use JTAG to quickly extract data from a DUT to perform low-level data extraction to pinpoint SEE induced errors, or inject data into a DUT to emulate a SEE test environment and to verify mitigation techniques and system responses before SEE testing. A test station, utilising a Raspberry Pi, is designed to interface with the DUT while inside the SEE test radiation vault and has the option of controlling power to the DUT as well. A monitoring station is also implemented that allows the tester to interface to the test station from a computer over ethernet, enabling safe operation of the test station and DUT from outside the vault. The design is easily changeable to allow for different testing styles or DUTs. Before the final iteration, it was also subjected to a real SEE test at iThemba Labs to verify its effectiveness. A scripting ability was also added, allowing for automated tests that can be useful to increase testers' effectiveness during SEE testing or to use fault injection to determine areas sensitive to errors inside DUT implementations or to test the effectiveness of implemented mitigation techniques.
- ItemDevelopment of a radiation resistant communication node for satellite sub-systems(Stellenbosch : Stellenbosch University, 2014-04) Thesnaar, Emile Jacobus; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: Within a complex electronic system, sub-system communication forms the backbone of the functionality of any satellite. It allows multiple processors to run simultaneously and data to be shared amongst them. Without it, a single processor would have to control the entire satellite. Not only would such a design then be overly complicated, but the processor would also not have sufficient capacity to service all the components efficiently. Furthermore the detrimental effects that radiation have on integrated circuits are well documented and can be anything from a single bit flip to a complete integrated circuit failure. If not repaired, a failure on a sub-system communication bus could lead to the loss of the entire satellite. Die goal is to create more radiation resistant Controller-Area-Network (CAN) node. Since a full triple modular redundant design will have a large footprint and high power consumption, a combination of techniques will be applied and tested. The goal is to achieve improved footprint utilisation over triple modular redundancy, while still maintaining good resistance to Single Event Upsets (SEU). By applying simulation, it was sufficiently proven that the implementation of the individual techniques used functioned according to expectations. These techniques included error detection and correction using Hamming Codes, single event transient filter and triple modular redundancy. Having applied these mitigation techniques, the footprint of the CAN controller increased by only 116%. Simulation showed that the Error Detection and Correction and Triple Modular Redundancy worked effectively with the CAN controller, and that the CAN controller could function as originally intended. Using radiation testing, the design proved to be more resistant to SEUs than the unmitigated CAN controller. It was thus shown that through using a combination of mitigation techniques, it is possible to develop an optimal design with a high level of resistance against Single Event Upsets, utilizing a smaller footprint than implementing Triple Modular Redundancy.
- ItemDevelopment of a satellite network simulator tool and simulation of AX.25, FX.25 and a hybrid protocol for nano-satellite communications(Stellenbosch : Stellenbosch University, 2014-12) Le Roux, Jan-Hielke; Barnard, Arno; Wolhuter, R.; Stellenbosch University. Faculty of Engineering. Department of Electrical and Electronic Engineering.ENGLISH ABSTRACT: Nano-satellites are mostly used in lower earth orbit applications, where communication intervals are limited, often to a combined total of less than one hour per day. With these type of inherent limitations of lower earth orbits, there are also the physical size and equipment restriction of nano-satellites to consider, especially those of the CubeSat specification. It is of critical importance to use the limited time and communication resources as effectively as possible. The network protocol has a huge influence on reliability and throughput of a satellite network. An important requisite for designing, comparing and improving network protocols is a network protocol simulator, that is able to envisage the design results. Simulation can facilitate rapid development and unforeseen discoveries. Very little information is currently available regarding communication protocols used in nano-satellites. This thesis aims to explore and improve the current status of nano-satellite network simulation, as well as to demonstrate the development of an improved communication protocol strategy. It was found that there is a lack of proper simulation tools for satellite networks, which led to the development of SatSim. SatSim is a discrete event network simulation tool, developed in Python, which can be used to develop and analyse network protocols. SatSim was verified by comparing simulation results with other published results, which made use of different software tools and theoretical throughput calculations. AX.25 is one of the most commonly used network protocols in the nano-satellite industry. It was implemented in SatSim and verified with theoretical throughput calculations, as no other simulation data on AX.25 was available. AX.25 was used as a baseline protocol to improve upon. FX.25 was developed by the Stensat Group in an attempt to improve AX.25. FX.25 adds forward error correction to AX.25, by wrapping additional data around the AX.25 frames. This method maintains backward compatibility with AX.25. FX.25 was implemented in SatSim and the simulation results proved that FX.25 was a more reliable protocol than AX.25, as it can communicate at lower elevations and over noisier communication channels. However, the drawback of the additional forward error correction is the increased overhead, which reduces the overall payload data throughput. A modular AX/FX.25 protocol was then implemented in SatSim, to exploit the strengths of both protocols. This hybrid protocol yielded significant improvements to data throughput and can enable future software defined radio or hardware developments.
- ItemEvaluation of VANET standards and protocols for distributed licence plate detection and reporting(2019-12) Truter, Jacobus Christoffel; Engelbrecht, H. A.; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: Implementation and evaluation of existing VANET standards and protocols for suitability of distributed licence plate detection and reporting in an urban scenario was the problem this project set out to investigate. Simulation was used to approach the problem since large scale deployment of commercially available VANET hardware was not feasible. A simulation environment providing realistic wireless networking and vehicular tra c patterns with which to evaluate VANET standards and protocols was successfully realised. An open source, Linux-based hardware solution (VANET OBU fully implementing IEEE 802.11p and AODV was created. Core aspects of the network simulation environment was successfully veri ed and calibrated by means of experimentation with the hardware solution. A distributed licence plate detection application was implemented in the veri ed and calibrated simulation environment, and analysis of large scale simulations resulted in the conclusion that IEEE 802.11p and AODV is suitable for distributed license plate detection and reporting as per its implementation in this project.
- ItemFast star tracker hardware implementation and algorithm optimisations on a system-on-a-chip device(2019-12) Von Wielligh, Christiaan Lodewyk; Visagie, Lourens; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: Star trackers are instruments used onboard a spacecraft that utilize digital image sensors, optics and digital hardware to determine the inertial attitude of the spacecraft. Currently, these star trackers are the most accurate sensor system used onboard a spacecraft ADCS (attitude determination and control system). The majority of space missions requires high precision attitude determination which stresses the need for star trackers. Modern ADCS's, especially when making use of Control Moment Gyros (CMG's), demand fast update rates for increased agility. Star detection, a process where centroid locations are extracted from a star image, takes significant time in the star tracker pipeline. This is due to a large number of pixels that needs to be processed, causing a high computational burden on conventional microprocessors. We propose a solution where centroid extraction is implemented through novel design on an FPGA. This architecture makes it possible to extract centroid locations at the same time as the image data is streamed from the sensor. Such parallelization significantly increases the update rate of the star tracker without compromising accuracy or power usage. The final design is implemented on a Xilinx Zynq SoC (System-on-a-Chip) device, which includes an FPGA and ARM processor. Tests are performed using simulated night sky images, real star images and a live sensor. Optimized matching algorithms are implemented on the processing system and validated independently. Distortion correction and QUEST is implemented, and a fully autonomous, end-to-end star tracker, with 10 Hz update rate is demonstrated under the night sky.
- ItemFault Injection based Sensitivity Analysis to aid Robust Satellite Software Development(Stellenbosch : Stellenbosch University, 2023-03) Pheiffer, Clayton James; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: This thesis details a study on software fault injection as a means to aid robust satellite software development. The extensive effects ionizing radiation impose on modern silicon devices motivates the need for various testing methods against these effects, for a satellite under development. Commonly, particle accelerator facilities are used to carry out most of this type of testing. However, these facilities are often costly to run and difficult to access. Since some effects of ionizing radiation may be induced through other means, software fault injection is explored as a tool to simulate some of these effects in a target STM32 microcontroller, based on the Arm Cortex-M4 architecture. A lightweight software fault injection campaign, based on open-source libraries, is created and tested. The target microcontroller is loaded with modified versions of commonly used matrix multiply and quicksort benchmark software so that the campaign design can be verified with predictable outputs. The outputs of the campaign show that the software fault injection campaign fulfils its designed task; and that the data produced by the campaign can be used to analyse microcontroller performance and subsequently inform robust software design.
- ItemFirmware and functional test platform developed for a smart controller(Stellenbosch : Stellenbosch University, 2017-12) Naude, Nicolaas Hendrik; Booysen, M. J.; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: Natural resources are important for human existence. Initiatives to manage resources effectively are exercised daily. The consumption of water and electricity increases daily in South Africa, and worldwide, thus the need for exploring new resource savings techniques. The primary electricity supplier of South Africa, Eskom, can not meet the current demand at all times. Not only is South Africa facing a shortage of electricity supply, but, at the time of writing, also a drought that could harm the economy. The Western Cape and the Eastern Cape provinces are especially under pressure by the drought. The Western Cape government implemented water usage limits and it is currently escalated to 87 L per person per day. The Nelson Mandela Bay municipality, in the Eastern Cape, was on the verge of being declared a drought disaster area in March of 2017. The necessity of saving initiatives are thus evident for South Africa. The Internet of Things is well suited to contribute to these savings initiatives. This thesis forms part of a smart controller (SC) for electric water heaters (EWHs), which allows the user to monitor water usage and set a control schedule to automatically switch the EWH on and off. The SC gathers data from EWHs, allowing research to predict optimal heating schedules. This research can also be used to implement a scheduling technique to switch an EWH on and off, depending on the national electricity grid load during peak consumption times, whilst still providing the EWH user with hot water on demand. The first development in this thesis is focused on designing and implementing firmware for a new SC hardware design. The SC communicates to a central database, with the use of an equipped cellular modem. The firmware consists of two parts, modem firmware and peripheral firmware. The peripheral firmware is responsible for correct actuator function and measuring the sensors accurately. The measurements are aggregated and concatenated into a single report string, which is sent to a cloud based database every minute. The SC forms part of a smart electric water heater controller project, which received funding from the Water Research Council to develop and install SCs in eMkhondo municipality district in Mpumalanga, South Africa. The SC used for research purposes is upgraded with new hardware, containing a new processor, which lead to the requirement of new rmware. The new hardware was tested in-house by a labourer, which required technical skills. This test required physical signal injection and result evaluation by the tester. The need to improve this test procedure lead to the second development of this thesis. An automatic test procedure is designed, which consists of test hardware and test software. The implementation of the complete test system is evaluated and the system efficacy is determined. The research objective to develop and implement firmware for the new SC hardware is achieved and is implemented on a total of 245 SCs. The data collected, by these SCs, was of such a standard that research could be done on optimisation of heating schedules and provide a means to create awareness of a household's EWH consumption patterns. The second objective to develop and implement a test system was achieved, where the accuracy of the hardware is determined and the test system efficacy showed, during the validation tests, six of the ten tests were successful. The test system would be a benefit to small scale production sectors, where uncertified test equipment suface and cost effective test solutions are required.
- ItemFPGA implementation of a network coding capable switch(Stellenbosch : Stellenbosch University, 2020-03) De Villiers, Daniel Bernard Beaumont; Engelbrecht, H. A.; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: The amount of internet connected devices is expected to increase dramatically in the near future. This is especially due to the widespread use of Internet of Things (IoT) devices. The Fifth-Generation (5G) of cellular network technologies aims to facilitate in the rapid expansion of IoT devices by providing an increased data rate, higher throughput, device capacity and connection reliability. In order for 5G to be fully integrated into existing telecommunication system, many new technologies are being developed. Two technologies to help make 5G a reality are network coding and Software Defined Networking (SDN). Network coding is an alternative approach to traditional packet forwarding. Traditional packet-based networks use a “storeand- forward” approach, where intermediate nodes relay or replicate incoming information. Network coding provides an additional step and performs coding on the incoming data, known as “compute-and-forward”. SDN is another widely adopted network technology required for 5G. SDN segregates the traditional decentralized networking approach, into control and data processes. A software component is installed on each data forwarding device as the dataplane. The dataplane is the fast component of the network and is where all packet processing is conducted. The dataplane devices are controlled by centralised controller devices. The controllers have a “birds-eyeview” of the entire network and can therefore make more informed network processing decisions, compared to traditional networking. Multiple software implementations of network coding have been developed and implemented. Network coding has been integrated into SDN in emulated and software environments. There exist many hardware devices that support SDN protocols such as OpenFlow. However, there are no commercially available network hardware devices that support network coding. Researchers in the field of computer networking have to modify existing devices to include network coding functions. Network hardware devices are often proprietary and therefore it is difficult to modify existing devices to add custom features and functions, such as network coding. This thesis solves these problems by implementing a network coding capable switch in both a software and hardware based environment. The software based network coding functions are created as Virtual Network Functions (VNFs) that are deployed in an SDN environment as required. The hardware based network coding functionality is implemented using a Field Programmable Gate Array (FPGA) device. Both software and hardware implementations are integrated together using the OpenFlow based SDN bridge, Open vSwitch (OvS). The overall platform is designed to run on a general purpose PC and allows network coding to be evaluated in both physical and virtual network environments, with physical and Virtual Machine (VM) hosts. The network coding implementations are evaluated using a real packet based network. The VNF based network encoder and decoder achieve a coding throughput of 164.67 and 87.99 Mbps respectively. The FPGA based network encoder and decoder are able to achieve a coding throughput of 223.16 and 496.40 Mbps respectively, providing a speedup of 1.36 and 5.71 over the VNF based implementations. The FPGA logic is run using a single PCIe lane and 50Mhz clock frequency. Taking full advantage of the FPGA device resource utilization, all four possible PCIe lanes and the maximum clock frequencies, the encoder and decoder functions could be implemented to achieve a coding throughput of 1.5 and 2.96 Gbps respectively. The thesis demonstrates that FPGA based network coding is feasible and provides a significant performance increase over software based implementations. The performance however is reduced dramatically when integrated with a real packet based network. Future work should focus on optimising the integration between OvS and the network coding functions. This would hopefully alleviate any potential integration bottlenecks.
- ItemAn FPGA-based adaptive forward error correction protocol for cubeSats(Stellenbosch : Stellenbosch University, 2017-03) Mkhaliphi, Sandile; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: CubeSats have become popular due to their simplified model that reduces development time and costs. The standard, however, suffers from limitations imposed by the small form factor. Research is undertaken at different levels to improve the performance of CubeSats, of which one is on the communication subsystem. The question is how the throughput per satellite-to-ground communication session can be improved using modified error correction methods. Previous work at the ESL proposed a hybrid protocol design of the AX.25 and the FX.25, known as the AFX.25, whose simulation results suggested improved performance over pure protocol implementations. The AX.25 protocol has an error checking functionality but without error correction, so the FX.25 was introduced as a wrapper to the AX.25 to provide for error correction. Inasmuch as the AX.25 is popular among university CubeSat designs, it was necessary that an investigation be done to evaluate if it was the best choice of implementation. The CCSDS Telecommand protocol was chosen for performance evaluation against the AFX.25 due to its functionality which is closer to the FX.25. The evaluation was based on simulation and hardware complexity analysis. SatSim was used as a satellite network simulation environment. The results showed that the AFX.25 is a better choice over the CCSDS TC. The AFX.25 hardware design and implementation was therefore considered on a Field Programmable Gate Array (FPGA). The FPGAs’ parallel processing capability makes them an attractive choice of implementation for error encoding and decoding. The adaptive protocol was designed to switch between no error correction (AX.25) and error correction (FX.25) where the number of correctable errors is 8 using the Reed Solomon code (255, 239). The switching from AX.25 to FX.25 is determined by the packet loss rate while switching from FX.25 to AX.25 is influenced by the packet success rate. The system was implemented on a FusionM1AFS1500 development board interfaced with a half duplex RF board. Tests were carried out successfully on a terrestrial testbench which modelled a typical satellite pass.
- ItemHigh frame rate marker detection for single camera-based localisation(Stellenbosch : Stellenbosch University, 2022-04) Pretorius, Schalk; Jordaan, Willem; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: Localisation is a fundamental component of autonomous navigation. Au tonomous systems that perform high accuracy tasks require position and ori entation information at high rates. Pose information at high rates allows an autonomous system to react faster to changes in the environment and increases the accuracy and stability of the system. Current implementations of landmark-based localisation by using fiducial markers have a limited utility due to low detection and pose estimation rates. Increasing the frame rate that fiducial marker systems can run at greatly in creases the utility of these systems. The goal of this thesis was to design and implement a fiducial marker de tection system that runs on a low-power-, light-weight- and compact hardware platform that can operate at frame rates larger than 60 Frames Per Second (FPS) without compromising pose accuracy. The project goal was achieved by researching existing marker systems and implementations, designing a marker detection concept, implementing the con cept design on the chosen hardware platform and testing and verifying the implemented system. This thesis presents a high frame rate marker detection system that is designed to run on a ZYNQ 7020. The ZYNQ 7020 is a System on a Chip (SoC) consisting of a Field Programmable Gate Array (FGPA) and a Central Processing Unit (CPU). The marker detection system achieves a higher frame rate at comparable accuracy to existing systems by utilising the advantages of an FPGA. The FPGA is utilised to parallelise image processing functions and accelerate the data intensive image processing system. By using in-line processing to ex tract image information without first needing to store the image in memory processing time is reduced. The presented marker detection system has a comparable accuracy to other fiducial marker detection systems validating the performance of the proposed system. The designed and implemented system is tested and the system is verified to operate at an average framerate of 134 FPS.
- ItemLow cost sensor monitoring using mesh connected ultra-low power long-range transceivers(Stellenbosch : Stellenbosch University, 2023-12) Goos, Pieter; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: The deployment of a sensor monitoring, or telemetry, system can reduce the upkeep cost and time investment for a farmer in the rural agricultural sector. This thesis investigates the design of a relevant network simulation tool and physical test platform. Several networking terms are discussed and used to compare and select applicable mesh routing protocols. The AODV protocol is selected, and investigated, for implementation into the remaining components of this research. Network simulation tools are investigated to predict and minimize real world deployment issues. SatSim is selected and modified f or i ncreased terrestrial link accuracy by introducing a new signal propagation simulation tool. The simulation results are compared to measured, real world, values to show their accuracy and performance. Mesh network node hardware is designed, and built, to meet low power, low cost, and long transmission range requirements. A large focus is placed on component selection. The hardware performance is characterised to prove its ability. Firmware is designed to implement a modified AODV p rotocol. Its performance is then compared to the relevant routing standard and simulator results. The results prove the designed system is functional with SatSim acting as an effective n etwork p lanning t ool. Recommendations f or i mprovements are also made.
- ItemParallelising inference on cluster graphs(Stellenbosch : Stellenbosch University, 2020-12) Verburgh, Cornel; Du Preez, Johan; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: Cluster graphs (CGs), a technique used in machine learning, are computationally very complex and often are slow to converge to an answer. There are also various approaches that lead to convergence. Some approaches converge faster than others. However, finding the optimal approach is non-trivial. We investigated the use of a new parallel inference algorithm, comparing it to the current state of the art inference algorithms, such as parallel splash belief propagation and residual belief update. These were tested on several CGs, ranging from a simple sudoku solver to a PGM that does satellite image denoising. The results from these tests were as follows: for satellite image denoising a 5.3 times speedup was achieved, plateauing at 10 threads; for the sudoku solver the speedup ranged from 2.0 times to 4.0 times speed-up, normally plateauing around six threads. From the results it is clear that the algorithms perform better the more clusters are present. It is also important to note that hyperthreading affects the speed-up, as is shown by the reduction in CPU instructions per cycle the more threads are being used.
- ItemSatellite network simulator - design and verifcation using AODV and AntHocNet(Stellenbosch : Stellenbosch University, 2017-03) Merts, Andre-Jan; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: As access to space increases, the viability of creating satellite networks and dedicated services for satellite clients also increases. However, satellites are expensive to launch and cannot be easily maintained once in orbit, making it beneficial to simulate network performance before launch. Furthermore there is an extensive wealth of research regarding routing protocols available for terrestrial networks that have not been fully researched for satellite networks thus creating a need for a satellite network simulator. Any network has various ways in which its properties can be interpreted, which means any network metric must be unambiguously defined. Routing protocols can be classified in various ways, showing their inherent advantages, disadvantages, requirements and limitations. Combining these properties with information on the components of routing protocols, an analysis of routing protocols can be made and candidate routing protocols can be chosen. For this research AODV was chosen to allow functional verification and AntHocNet was chosen to show that the simulator is flexible enough to simulate various routing protocol functionality. Satellite networks were manually analysed with attention given to the key differences between terrestrial and satellite networks. Using this information in conjunction with previous research findings and recommendations, a vast distributed network similar to the Iridium network was chosen as a verification scenario for the simulator. A previously proposed network, called the OuterNet, was chosen to further research the transferability of AODV and AntHocNet to other satellite constellations. The expansion of SatSim from a basic point-to-point simulator to a network simulator capable of handling complex routing protocols was documented in detail, with clear information given as to which design choices were made and why. The key design drivers were user-friendliness, modularity and re-usability, and the code was structured to allow users to easily adjust and expand the simulator as needed. Due to the limited replicatable results, further testing for the MAC layer channel access for AODV and AntHocNet implementations was performed. SatSim was successfully expanded to allow for satellite network simulations. Preliminary findings regarding the suitability of AODV compared to AntHocNet for two different satellite constellations are presented.
- ItemA Study of optoelectronic and environmental factors affecting the accuracy of vehicle-mounted licence plate recognition(Stellenbosch : Stellenbosch University, 2019-04) Rademeyer, Martin Christian; Booysen, M. J.; Barnard, Arno; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: Across the world, licence plate recognition (LPR) technology has been used to combat vehicle-related crime in urban areas. However, commercially available LPR systems are expensive and not feasible for large scale adoption in developing countries. The development of a low-cost system will require an informed approach to selection of an appropriate camera, as well as a realistic understanding of the system's performance under various conditions. This work investigated the effect of optoelectronic and environmental factors on the ability of vehicle-mounted LPR systems to correctly identify licence plates. A theoretical LPR camera model was developed to estimate the effect of different cameras, while the effects of motion, orientation and lighting were evaluated in a series of experimental tests. The most influential optoelectronic factors were shown to be focus, focal length and image sensor resolution. Licence plates could theoretically be recognised across a large area using a fixed-focus prime lens mounted on a high-resolution image sensor. Furthermore, recognition was impaired during high-speed turn manoeuvres, as well as in cases where licence plates were orientated at more than a 45° angle to the camera. In night-time conditions, retroffective licence plates could be recognised at a distance comparable to that of daytime conditions, while oncoming headlights were shown to hinder accurate recognition. The optoelectronic model proved useful for selection of a cost-effective camera for use in an open source LPR system. Moreover, the study of environmental factors provided valuable insight into the limitations of LPR systems in various environmental and traffic conditions.
- ItemSub-pixel image translation estimation on a nanosatellite platform(Stellenbosch : Stellenbosch University, 2019-04) Jurgen, Ludemann; Barnard, Arno; Smit, W.; Malan, D. F.; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.ENGLISH ABSTRACT: Nanosatellites are limited in their physical size, which limits the physical size of payloads they can carry, thereby limiting the quality of images taken during CubeSat Earth Observation missions. Algorithms exist that combine partially overlapping images to produce better output image quality. These algorithms may either improve the signal-to-noise ratio via averaging, increase resolution via super-resolution or merely remove redundant information via mosaicing. Typically, they only function properly if the geometric transformations between consecutive images are known with high accuracy. They can either be applied terrestrially or on-board a satellite. Downloading large raw image data sets for terrestrial processing is impractical for a CubeSat mission, and therefore an on-board solution is desirable. This thesis discusses the accurate determination of the transformation between consecutive images on-board, laying the foundation for e cient onboard de-noising, super-resolution and mosaicing. Two common methods used to determine translation { normalised cross correlation (NCC) and phase correlation { are investigated. From simulated results, NCC is shown to be the better candidate for our application. NCC achieves sub-pixel accuracy by making use of polynomial least squares regression. NCC is well suited for implementation on a satellite platform where images are captured in quick succession, resulting in partially overlapping images with little rotation between frames. We compare two potential hardware platforms { the MicroZed 7020 and Jetson TK1 { and then describe how we implemented our proposed solution onto the former, using a hardware description language. Software simulation and rmware-implementation results, using simulated data, are compared and discussed. Subsequently, the MicroZed 7020's implemented design is characterised, compared and discussed in terms of algorithm and platform performance.