On designing sigma-delta converter systems for class-D power amplifiers
We analyze sigma delta converters and present a method to design digitally driven class-D (PWM) amplifiers that achieve specific signal to noise ratios. This method allows a simple tradeoff between the order of the sigma-delta converter and the increased sampling rate to be made to achieve the design goals. We demonstrate that this approach can be efficiently implemented in FPGA's and a modest DSP processor chip. This paper also presents a clarification and correction to the techniques proposed by Uchimura et al..