Low impedance characterisation and modeling of high power LDMOS devices

Malan, Pieter Jacob De Villiers (2005-12)

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005.


In RF power transistor characterisation, the designer is confronted with low impedance measurements (typically from 1 Ohm to 12 Ohm). These transistors are contained in metal-ceramic packages of which the lead widths vary with power capability. This thesis presents a high-quality fixture design with low impedance TRL calibration standards for characterisation of an LDMOS transistor. Pre-matching networks are used to transform to the low impedance environment. Since these pre-matching networks are independent of the termination impedance, the low impedance port can always be designed to comply with the same dimension as the device which is being measured.

Please refer to this item in SUNScholar by using the following persistent URL: http://hdl.handle.net/10019.1/2510
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