Monte Carlo optimization of superconducting complementary output switching logic circuits
Date
1998
Authors
Jeffery M.
Perold W.J.
Wang Z.
Van Duzer T.
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Abstract
The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix. © 1998 IEEE.
Description
Keywords
Computer simulation, Integrated circuit testing, Logic circuits, Logic design, Monte Carlo methods, Optimization, Timing circuits, Complementary output switching logic (COSL), Multivariable threshold logic (MVTL) circuits, Software package HSPICE, Superconducting integrated circuits, Superconducting devices
Citation
IEEE Transactions on Applied Superconductivity
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