Modeling superconducting components based on the fabrication process and layout dimensions
A procedure is described where the mask dimensions of superconducting components are used in SPICE simulations to predict the performance of a device. Thickness tolerances of the fabrication process, as well as mask bias offsets and mask tolerances are included in the component models. This makes it possible to predict circuit yield by Monte Carlo analyses, which are based on the fabrication process design rules. Model descriptions of all the components used in a standard superconductor multilayer process are given, and the accuracy of the models are verified. The superconducting components that are modeled include microstrip transmission lines, coupled transmission lines, resistors and Josephson junctions. The usefulness of this procedure is demonstrated by simulation results of a stack amplifier, where the yield of the circuit is calculated for the lumped element model and the proposed model, which includes parasitic elements.