Optimised asynchronous timing for superconductive digital circuits
Date
2006
Authors
Gerber H.R.
Fourie C.J.
Perold W.J.
Journal Title
Journal ISSN
Volume Title
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Abstract
Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of Gigahertz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and a asynchronous full adder was implemented and tested. Copyright © 2004 IEEE.
Description
Keywords
Asynchronous logic, Asynchronous timing, Clock distribution, Clock signal, Complex problems, Full adders, Low power application, Optimal timing, Rapid single-flux quantum logic, RSFQ circuits, Self-timing, Semiconductor design, Semiconductor technology, Superconducting electronics, Synchronous clocking, Ultra high speed, Adders, Digital integrated circuits, Electric clocks, Integrated circuits, Logic gates, Semiconductor device manufacture, Superconductivity, Time measurement, Timing circuits, Logic circuits
Citation
Transactions of the South African Institute of Electrical Engineers
97
3
97
3